Efficient arithmetic on ARM-NEON and its application for high-speed RSA implementation

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Efficient arithmetic on ARM-NEON and its application for high-speed RSA implementation

Advanced modern processors support Single Instruction Multiple Data (SIMD) instructions (e.g. Intel-AVX, ARM-NEON) and a massive body of research on vector-parallel implementations of modular arithmetic, which are crucial components for modern public-key cryptography ranging from RSA, ElGamal, DSA and ECC, have been conducted. In this paper, we introduce a novel Double Operand Scanning (DOS) me...

متن کامل

NEON-SIDH: Efficient Implementation of Supersingular Isogeny Diffie-Hellman Key Exchange Protocol on ARM

In this paper, we investigate the e ciency of implementing a post-quantum key exchange protocol over isogenies (PQCrypto 2011) on ARM-powered embedded platforms. This work proposes to employ new primes to speed up constant-time nite eld arithmetic and perform isogenies quickly. Montgomery multiplication and reduction are employed to produce a speedup of 3 over the GNU Multiprecision Library. We...

متن کامل

Cryptography for ARM NEON

Recent research has shown that implementations with variable execution timing may allow attackers to extract secret cryptographic keys stored on the device. Timing variances can occur due to implementation choices (e.g. data-dependent branches) or due to the internal architecture of the processor core (e.g. cache lines). In order to overcome this problem one needs to find alternative implementa...

متن کامل

The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip

The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder Theorem (CRT) for the private key operations. This paper presents the multiplier architecture of the RSA crypto chip, a high-speed hardware accelerator for long integer modular arithmetic. The RSA multiplier datapath is re...

متن کامل

High Speed and Area Efficient Fpga Implementation of Fir Filter Using Distributed Arithmetic

In this paper, high speed and area efficient multiplier-less architecture for Finite impulse response filter (FIR) based on distributed arithmetic is presented. The proposed Lookup table less architecture for FIR filter uses the speed advantage of Carry save adder. A modification in the shift accumulator stage yields both high speed and area savings. Furthermore, Memory reduction is possible si...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Security and Communication Networks

سال: 2016

ISSN: 1939-0114

DOI: 10.1002/sec.1706